1. Field of the Invention
The present invention relates to a semiconductor device including a plurality of metal-oxide-semiconductor transistors and to its fabrication method.
2. Description of the Related Art
Reduction of the size and cost of electronic devices calls for further downsizing of the power transistors included in such electronic devices. For mobile devices and home appliances a particular need is to integrate control circuits and a plurality of power transistors onto the same semiconductor substrate. In integrated devices of this type, isolation becomes an issue. Known methods of isolating different circuit elements formed on the same semiconductor substrate include local oxidation of silicon (LOCOS) and shallow trench isolation (STI).
In addition to downsizing and higher integration, higher-voltage semiconductor devices are being required. Semiconductor devices that can withstand higher voltages can conduct more driving current. High-voltage semiconductor devices are also resistant to current leakage and latch-up. The voltage withstanding requirements for typical semiconductor devices are a few volts for microcomputer and memory devices, including dynamic random access memory (DRAM), several tens of volts for liquid crystal display drivers, and several hundred volts for high-voltage displays.
Exemplary high-voltage metal-oxide-semiconductor (MOS) transistors and their fabrication methods are disclosed by Fujita in Japanese Patent No. 3221766 and by Oyanagi et al. in Japanese Patent Application Publication No. 2002-270825.
Fujita teaches covering parts of the lightly doped source and drain diffusion layers of a MOS transistor with a resist layer to suppress the increase in their doping concentration when the more heavily doped source and drain regions are formed, and combines this technique with precise control of the size of the lightly doped regions to ensure a reduction in gate overlap capacitance. Fujita also teaches a self-aligned technology in which parts of the lightly doped source and drain diffusion layers are covered by sidewalls that control their size accurately.
Oyanagi et al. teach forming an electric field relaxation layer that overlaps the gate electrode from the drain side and forming the highly doped drain layer at a distance from the gate oxide layer, thereby improving the source-drain breakdown voltage and reducing the gate length.
One common type of semiconductor device using high-voltage MOS transistors is a booster circuit that converts a low input voltage to a high output voltage. This type of booster circuit includes both low-voltage MOS transistors on the input side and high-voltage MOS transistors on the output side. The high-voltage MOS transistors improve the reliability of the device by increasing its breakdown voltage.
The high-voltage (high source-drain breakdown voltage) MOS transistors used in booster circuits have thicker gate oxide layers than do general low-voltage MOS transistors. Since drain current is inversely proportional to gate oxide thickness, it is difficult to obtain drain current efficiently from these high-voltage MOS transistors. To compensate for the increased gate oxide thickness, the gate width has to be increased, making it difficult to reduce the size of the booster circuit.